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Lam Research 714-131255-001-B Key Component
Lam Research 714-131255-001-B
Product Overview
The Lam Research 714-131255-001-B is an ultra-high-purity core consumable component of the process kit, specially designed for the reaction chambers of semiconductor plasma etching equipment. Installed closely around the edge of the Electrostatic Chuck (ESC) in Lam Research etching tools, this component forms a critical physical boundary for plasma confinement and electric field modification inside the reaction chamber.
Far from a simple mechanical shielding ring, it is a precision-engineered specialty component manufactured with strict resistivity control, optimized high thermal conductivity, and ultra-high material purity. Its core function is to regulate the RF electric field distribution at the chamber edge and compensate for plasma density attenuation caused by wafer edge effects through its unique geometric profile and conductive properties.
In ultra-high aspect ratio etching for 3D NAND devices and atomic-level precision dielectric etching for advanced logic chips, the surface condition and geometric accuracy of this component directly determine the edge-die etching rate, selectivity, and critical dimension uniformity. It serves as an indispensable core part for improving overall wafer yield, especially edge yield.
As a periodically replaceable consumable spare part belonging to Lam Research’s highly customized process kit system, its service life is measured by cumulative RF hours or the total number of processed wafers. Fabricated from high-purity, high-density silicon or advanced Silicon Carbide (SiC) materials via precision machining and ultra-clean cleaning processes, the component features specialized passivation and polishing surface treatment.
Product Specifications
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Parameter Name
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Parameter Value
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Product Model
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Lam Research 714-131255-001-B
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Manufacturer
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Lam Research
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Product Type
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Reaction Chamber Process Kit Component (Focus Ring / Edge Ring)
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Main Material
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High-purity Monocrystalline/Polycrystalline Silicon or Silicon Carbide (SiC) (customized per process requirements)
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Material Purity
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＞99.999% (5N+ grade, strict control of trace metal impurities)
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Resistivity
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0.005 ~ 20 Ω·cm (adjustable per specific process recipes)
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Thermal Conductivity
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＞150 W/(m·K) (SiC) / Approximately 150 W/(m·K) (Silicon)
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Surface Roughness
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Ra ＜ 0.8 μm (plasma contact surface with specialized textured treatment)
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Geometric Accuracy (Flatness)
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＜ 50 μm (ensures precise fitting with ESC assembly)
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Operating Temperature Range
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Ambient to 350°C (for chamber high-temperature baking and process operation)
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Applicable Gas Environment
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Fluorine/Chlorine/Bromine-based plasma (CF₄, NF₃, Cl₂, HBr, etc.)
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Packaging Cleanliness Class
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Class 1 (double-bag sealed packaging with nitrogen protection)
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Typical Service Life
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5,000 ~ 20,000 RF Hours (dependent on process conditions)
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Matching Components
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Bushing, Insulator Ring, and other dielectric parts
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Storage Conditions
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Dry, clean, light-shielded, stored at room temperature
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Structure and Composition
The Lam Research 714-131255-001-B features a sophisticated structural design that integrates functional optimization, material science, and mechanical precision. Physically, it is a high-precision annular thin plate with customized step structures. Its inner/outer diameter, thickness, and chamfer dimensions are strictly calibrated to match the outer contour of the electrostatic chuck (ESC) and inner wall of the matched reaction chamber.
The plasma-facing upper surface is treated with sandblasting or laser etching to form a uniform microscopic textured morphology. This design increases the plasma contact area, optimizes the ion angle distribution at the wafer edge, enhances the adhesion of process by-products, and prevents large particle shedding that causes wafer contamination.
The component adopts ultra-high-purity raw materials with precisely controlled doping concentrations. According to different process conductivity requirements, it is available in doped conductive silicon, semi-insulating silicon, or high-performance Silicon Carbide (SiC) with higher thermal conductivity and superior erosion resistance. With no moving parts or electrical connections, its overall performance is entirely determined by the inherent physical properties (resistivity, thermal conductivity) and ultra-precise mechanical dimensions of the base material.
It forms a high-precision dimensional matching system with the lower ESC and upper focus/constraint ring. The component is positioned by gravity and precise gap fitting with surrounding parts without additional fasteners. This simple seated structure enables fast assembly and disassembly in cleanroom environments, shortens PM downtime, and eliminates metal contamination risks caused by fastener sputtering in plasma environments.
Key Features and Advantages
1. Ultra-High Purity and Ultra-Low Metal Contamination Risk
Manufactured with 5N+ ultra-high-purity base materials and implemented with strict full-process metal impurity control throughout machining, cleaning, and packaging procedures, this component effectively prevents heavy metal elements such as iron, copper, and nickel from being sputtered and redeposited on wafer surfaces during etching. It significantly improves Gate Oxide Integrity (GOI) and minority carrier lifetime, which is critical for boosting the electrical yield of advanced-node semiconductor chips.
2. Optimized Edge Electric Field Modulation Capability
With customized resistivity design, the component precisely couples RF bias to the wafer edge area. Acting as an “electric field lens”, it compensates for plasma sheath bending effects induced by geometric discontinuities at the wafer edge. It effectively mitigates wafer edge etching loading effects, narrows the distribution range of within-wafer Critical Dimension Uniformity (CDU), and substantially increases the number of valid edge dies per wafer.
3. Excellent Plasma Erosion Resistance and Long Service Life
Resistant to continuous bombardment by high-energy ions and active free radicals in the reaction chamber, the component delivers outstanding anti-corrosion and anti-sputtering performance. Its high-density structure and optimized surface morphology ensure uniform and slow material consumption, with minimal geometric profile variation throughout its service lifecycle. This maintains stable process parameters (etch rate, selectivity) between PM cycles, improves equipment uptime, and reduces Fab spare part procurement frequency and overall operational costs.
Applications
The Lam Research 714-131255-001-B is mainly applied to high-end plasma etching processes for 200mm and 300mm wafers, serving as a core part of the process kit for Lam Research 2300 series etching tools, including Kiyo series dielectric etchers, Flex series conductor etchers, and Exelan series metal etchers.
Its application scenarios cover anisotropic dielectric etching (silicon oxide/silicon nitride spacer etching), polysilicon gate etching, and via/trench etching for metal interconnects in logic chip manufacturing. For memory chips, it is widely used in ultra-high aspect ratio channel hole etching for 3D NAND flash and deep trench etching for DRAM capacitors, ensuring consistent structural precision at both wafer center and edge via edge electric field optimization.
It also supports power semiconductor and MEMS manufacturing processes such as TSV etching and deep silicon Reactive Ion Etching (DRIE). The component solves common edge-effect defects including edge etch overshoot and roll-off, and prevents edge die failure caused by abnormal wafer edge profiles. As a key monitored consumable for process stability evaluation, PM cycle definition, and edge yield improvement, it is widely deployed in advanced wafer fabs worldwide.
Related Products
- Lam Research 714-131255-000-A: Previous revision (Rev A) of the target model, with minor differences in material resistivity range or surface texture treatment. Mixed installation with the -B version in a single chamber is not recommended.
- Lam Research 714-131255-002-B: Upper coupling/constraint ring matching the 714-131255-001-B. The two components work together to form a complete plasma edge confinement and electric field correction system inside the chamber.
- Lam Research 714-131254-001-B: ESC surface focus ring for the same chamber, installed in nested up-down/inner-outer coordination with the 714-131255-001-B to jointly regulate edge plasma behavior.
- Lam Research 830-101215-102: High-precision ceramic (Al₂O₃/Y₂O₃) bushing exclusively matched with the target component. Installed below the 714-131255-001-B to provide electrical isolation and positional support.
- Lam Research 714-131256-001: Upper electrode silicon/quartz liner ring, which forms a complete gas flow and plasma guiding path with lower annular components.
- Lam Research 830-102200-001: Special clean wiping kit for component installation, including dust-free cloths and isopropyl alcohol, for cleaning ESC mounting surfaces.
Installation and Maintenance
Pre-Installation Preparation
Before installing the Lam Research 714-131255-001-B, confirm the reaction chamber has returned to atmospheric pressure and cooled to room temperature (or the safe chamber-opening temperature specified by processes). Ensure all upstream gas sources are shut off and the chamber is fully purged with nitrogen. Operators must wear complete cleanroom protective equipment (cleanroom suit, face shield, nitrile gloves) and perform all operations in a Class 1 microenvironment.
Handle the new component gently with clean gloves, avoiding contact with the plasma-facing working surface and sharp edges. Clean the ESC edge mounting steps and positioning pin holes with lint-free cloths dipped in electronic-grade isopropyl alcohol to eliminate residual particles. Place the 714-131255-001-B horizontally and slowly in place per positioning marks or standard orientation. Forcible pressing or inclined sliding is prohibited to prevent surface scratches or fitting surface damage.
Maintenance Guidelines
As a periodic consumable part, its replacement cycle shall be determined based on process recipes, cumulative RF operating hours, and regular wafer edge defect monitoring data. During each replacement, inspect the wear condition of the matched upper constraint ring and lower ceramic bushing, and replace them synchronously to ensure matching process performance.
Check the surface morphology (color variation, roughness change) and structural integrity (cracks, edge chipping) of the removed old component. Abnormal conditions are usually associated with abnormal chamber discharge or process parameter deviation, requiring root cause analysis. Waste components shall be recycled in accordance with Fab hazardous waste management regulations.
After installation, run at least one dummy wafer etching cycle for component seasoning to stabilize the surface state. Mass production wafer processing can only be resumed after process parameters reach a stable state.
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